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idt8slvp1104anlgi march 13, 2018 1 ?2018 integrated device technology, inc. datasheet low phase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8SLVP1104I description the idt8SLVP1104I is a high-performance differential lvpecl fanout buffer. the device is designed for the fanout of high-fr equency, very low additive phase-noise clock and data signals. the idt8SLVP1104I is characterized to operate from a 3.3v or 2.5v power supply. guaranteed output-to- output and part-to-par t skew characteristi cs make the idt8SLVP1104I ideal fo r those clock distribution applications demanding well -defined performance and repeatability.four low skew outputs are available. the integrat ed bias voltage reference enables easy interfacing of single-ended sign als to the device inputs. the device is optimized for low power consum ption and low additive phase noise. features? four low skew, low additive jitte r lvpecl differential output p airs ? differential lvpecl input pair ca n accept the following differe ntial input levels: lvds, lvpecl, cml ? differential pclkx pairs can a lso accept single-ended lvcmos levels. see the applications section writing the differential i nput levels to accept single-ended levels (figures 1 and 2) ? maximum input clo ck frequency: 2ghz ? lvcmos interface levels for th e control input (input select) ? output skew: 5ps (typical) ? propagation delay: 320ps (maximum) ? low additive phase jitter, rms; f ref = 156.25mhz, v pp = 1v, 12khz - 20mhz: 40fs (maximum) ? maximum device curr ent consumption (i ee ): 60ma (maximum) ? full 3.3v or 2.5v supply voltage ? lead-free (rohs 6) packaging ? -40c to 85c ambient operating temperature block diagram pin assignment idt8SLVP1104I 16 lead vfqfpn 3.0mm x 3.0mm x 0. 925mm package body 1.7mm x 1.7mm epad size nl package top view f ref pclk npclk v ref v cc q0nq0 q1 nq1 q2 nq2 q3 nq3 pulldown pullup/pulldown voltage reference 1 2 3 4 12 11 10 9 1314 15 16 87 6 5 q2 n q2 q3 n q3 v ref npcl k pclk v cc v ee nc nc nc q1 nq 0 q0 nq 1
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 2 ?2018 integrated device technology, inc. pin descriptions and characteristics table 1. pin descriptions note: pulldown and pullup refers to an internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v ee power negative supply pin. 2 nc unused do not connect. 3 nc unused do not connect. 4 nc unused do not connect. 5v cc power power supply pin. 6 pclk input pulldown non-inverting differentia l lvpecl clock/data input. 7n p c l ki n p u t pullup/ pulldown inverting differential lvpecl clock/data input. v cc /2 default when left floating. 8v ref output bias voltage refer ence for the pclk inputs. 9, 10 q0, nq0 output differential ou tput pair 0. lvpecl interface levels. 11, 12 q1, nq1 output differential ou tput pair 1. lvpecl interface levels. 13, 14 q2, nq2 output differential ou tput pair 2. lvpecl interface levels. 15, 16 q3, nq3 output differential ou tput pair 3. lvpecl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ?
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 3 ?2018 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are st ress specifications only. functional o peration of product at these c onditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to abs olute maximum rating conditions for extended periods may affect product reliability. note 1: according to jedec/jesd 22-a114/22-c101. dc electrical characteristics table 3a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 3b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 3c. lvpecl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc C 2v. item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma100ma input sink/source, i ref 2ma maximum junction temperature, t j,max 125c storage temperature, t stg -65 ? c to 150 ? c esd - human body model, note 1 2000v esd - charged device model, note 1 1500v symbol parameter test conditi ons minimum typical maximum units v cc power supply voltage 3.135 3.3v 3.465 v i ee power supply current 53 60 ma i cc power supply current q0 to q3 terminated 50 ? to v cc C 2v 170 204 ma symbol parameter test conditi ons minimum typical maximum units v cc power supply voltage 2.375 2.5v 2.625 v i ee power supply current 49 55 ma i cc power supply current q0 to q3 terminated 50 ? to v cc C 2v 170 199 ma symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 3.465v 150 a i il input low current pclk v cc = 3.465v, v in = 0v -10 a npclk v cc = 3.465v, v in = 0v -150 a v ref reference voltage for input bias i ref = 1ma v cc C 1.6 v cc C 1.3 v cc C 1.1 v v oh output high voltage; note 1 v cc C 1.1 v cc C 0.9 v cc C 0.7 v v ol output low voltage; note 1 v cc C 2.0 v cc C 1.65 v cc C 1.5 v
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 4 ?2018 integrated device technology, inc. table 3d. lvpecl dc characteristics, v cc = 2.5v 5%, v ee = 0v, ta = -40c to 85c note 1: outputs terminated with 50 ? to v cc C 2v. symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 2.625v 150 a i il input low current pclk v cc = 2.625v, v in = 0v -10 a npclk v cc = 2.625v, v in = 0v -150 a v ref reference voltage for input bias i ref = 1ma v cc C 1.6 v cc C 1.3 v cc C 1.1 v v oh output high voltage; note 1 v cc C 1.1 v cc C 0.9 v cc C 0.7 v v ol output low voltage; note 1 v cc C 2.0 v cc C 1.6 v cc C 1.5 v
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 5 ?2018 integrated device technology, inc. ac electrical characteristics table 4. ac electrical characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified a mbient operating temperature range, which is established when t he device is mounted in a test socket with maintained transverse airflow gre ater than 500 lfpm. the device will meet specifications after t hermal equilibrium has been reached under these conditions. note 1: measured from the differ ential input cro ssing point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differentia l crosspoints. note 3: this parameter is defined in accordance with jedec stan dard 65. notes continued on next page. symbol parameter test conditio ns minimum typical maximum units f ref input frequency pclk, npclk 2g h z ? v/ ? t input edge rate pclk, npclk 1.5 v/ns t pd propagation delay; note 1 pck, npclk to any q[0:3], nq[0:3] for v pp = 0.1v or 0.3v 120 200 320 ps t sk(o) output skew; note 2, 3 52 5p s t sk(p) pulse skew f ref = 100mhz 5 20 ps t sk(pp) part-to-part skew; note 3, 4 100 200 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section f ref = 122.88mhz sine wave, v pp = 1v, integration range : 1khz C 40mhz 170 fs f ref = 122.88mhz sine wave, v pp = 1v, integration range: 10khz C 20mhz 114 fs f ref = 122.88mhz sine wave, v pp = 1v, integration range: 12khz C 20mhz 114 fs f ref = 156.25mhz square wave, v pp = 1v, integration range : 1khz C 40mhz 42 51 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 10khz C 20mhz 32 40 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 12khz C 20mhz 32 40 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range : 1khz C 40mhz 51 71 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 10khz C 20mhz 38 52 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 12khz C 20mhz 38 52 fs t r / t f output rise/ fall time 20% to 80% 35 180 ps v pp peak-to-peak input voltage; note 5, 6 f ref < 1.5 ghz 0.1 1.5 v f ref > 1.5 ghz 0.2 1.5 v v cmr common mode input voltage; note 5, 6, 7 1.0 v cc C 0.6 v v o (pp) output voltage swing, peak-to-peak v cc = 3.3v, f ref ?? 2ghz 0.45 0.75 1.0 v v cc = 2.5v, f ref ?? 2ghz 0.4 0.65 1.0 v v diff_out differential output voltage swing, peak-to-peak v cc = 3.3v, f ref ?? 2ghz 0.9 1.5 2.0 v v cc = 2.5v, f ref ?? 2ghz 0.8 1.3 2.0 v
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 6 ?2018 integrated device technology, inc. note 4: defined as skew between outputs on different devices op erating at the same supply voltage, same frequency, same temper ature and with equal load conditions. usi ng the same type of inputs on ea ch device, the outputs are measured at the differential cross p oints. note 5: for single-ended lvcmo s input applications, refer to th e applications section writing the differential input levels to accept single-ended levels (figures 1 and 2). note 6: v il should not be less than -0.3v. note 7: common mode input voltage is defined as the crosspoint.
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 7 ?2018 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset from the fun damental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expresse d using a phase noise plot and is most often the specified plot in many applications. phas e noise is defined as the ratio of the noise power present in a 1hz ban d at a specified offset from the fundame ntal frequency to the power va lue of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. w hen the required offset is specifi ed, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundament al. by investigating jitter in the f requency domain, w e get a bette r understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to cal culate an expected bit error rate given a phase noise plot. as with most timing sp ecifications, phase noise measurements ha s issues relating to the limitati ons of the equipment. often the noise floor of the equipment is higher than the noise floor of the de vice. this is illustrated above. the devic e meets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. measured using a wenzel 156.25m hz oscillator as the input sourc e. offset from carrier frequency (hz) ssb phase noise dbc/hz f ref = 156.25mhz, v pp = 1v, integration range 12khz C 20mhz: 40fs (maximum)
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 8 ?2018 integrated device technology, inc. parameter measurement information 3.3v lvpecl output load test circuit differential input level part-to-part skew 2.5v lvpecl output load test circuit output skew pulse skew scope qx nqx v ee v cc 2v -1.3v0.165v v cc v ee npclk pclk t sk(pp) part 1 part 2 nqx qx nqy qy scope qx nqx v ee v cc 2v -0.5v0.125v nqx qx nqy qy t plh t phl t sk(p) = |t phl - t plh | npclk pclk nqy qy
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 9 ?2018 integrated device technology, inc. parameter measurement information, continued propagation delay out put rise/fall time t pd npclk pclk pclk q[0:3] nq[0:3] q[0:3]
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 10 ?2018 integrated device technology, inc. applications information wiring the differential input t o accept single-ended levels the idt8SLVP1104I inpu ts can be interfaced to lvpecl, lvds, cml or lvcmos drivers. figure 1a illustrates how to dc couple a single lvcmos input to the idt8SLVP1104I. the value of the seri es resistance rs is calculated a s the difference between the transmission line imped ance and the driver output impedance. th is resistor should be placed close to the lvcmos driver. to avoid cross-coupling of single-ended lvcmos signals, apply the lvcmos signals to no more t han one pclk input. a practical method to implement vth is shown in figure 1b below. the reference volt age vth = v1 = v cc /2, is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as cl ose to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position th e v1 in the center of the input voltage swing. for example, if the i nput clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v1 at 1.25v. the val ues below apply when both the single-ended swing and v cc are at the same voltage. figure 1a. dc-coup ling a single lvcm os input to the idt8SLVP1104I when using single-ended signalin g, the noise rejection benefits of differential signaling are reduc ed. even though the differentia l input can handle full rail lvcmos signaling, it is recommended that t he amplitude be reduced, p articularly if both input references are lvcmos to minimize cross talk. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. figure 1b shows a way to attenuate the pclk input level by a fa ctor of two as well as matching the transmission line between the lvcmos driver and the idt8slvp1 104i at both the source and the load. this configuration require s that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. r3 and r4 in parallel should e qual the transmission line impedance; for most 50 ? applications, r3 and r4 will be 100 ? . the values of the resist ors can be increased to reduce the loading for slower and weaker lvcmos driver. though some of the recommended co mponents of figure 1b might not be used, the pads should be placed in the layout so that they can be utilized for debugging purposes . the datasheet specification s are characterized and guaranteed by using a differential signal. figure 1b. alternative dc coupling a single lvcmos input to the idt8SLVP1104I rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r21k r11k c1 0.1uf ro + rs = zo v1 vc c vc c
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 11 ?2018 integrated device technology, inc. 3.3v lvpecl clock input interface the pclk /npclk accepts l vpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here a re examples only. if the drive r is from another vendor, use their termination recommendation. plea se consult with the vendor of the d river component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a cml driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by a 3.3v lvds driver figure 2b. pclk/npcl k input driven by a built-in pullup cml driver figure 2d. pclk/npcl k input driven by a 3.3v lvpecl driver with ac couple pclk npclk lvpecl input cml 3.3v 3.3v 3.3v r3125 r4125 r184 r284 3.3v zo = 50 zo = 50 pclknpclk 3.3v 3.3v lvpecl lvpecl input 3 . 3v r1 1 00 ? lvd s p c l k np c l k 3 . 3v lvpe c l in p u t z o = 50 ? z o = 50 ? pclknpclk 3.3v lvpec l input 3.3v zo = 50 zo = 50 r1100 cml built-in pullup
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 12 ?2018 integrated device technology, inc. 2.5v lvpecl clock input interface the pclk /npclk accepts l vpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here a re examples only. if the drive r is from another vendor, use their termination recommendation. plea se consult with the vendor of the d river component to confirm the driver termination requirements. figure 3a. pclk/npclk input driven by a cml driver figure 3c. pclk/npclk input driven by a 2.5v lvpecl driver figure 3e. pclk/npclk input driven by a 2.5v lvds driver figure 3b. pclk/npcl k input driven by a built-in pullup cml driver figure 3d. pclk/npcl k input driven by a 2.5v lvpecl driver with ac couple pclk npclk lvpecl input cml 2.5v 2.5v 2.5v 2.5v pclk npclk 2.5v 2.5v lvpecl lvpecl input pclk npclk pclk npclk 2.5v lvpecl input 2.5v cml built-in pullup
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 13 ?2018 integrated device technology, inc. recommendations for unused output pinsoutputs: lvpecl outputs all unused lvpecl outp uts can be left floating. we recommend th at there is no trace attached. both sides of the di fferential outp ut pair should either be left floating or terminated. vfqfpn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a la nd pattern must be incorporated on the printed circuit board (pcb) within the footprint of the pac kage corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, shoul d be at least the same size/sh ape as the exposed pad/slug area on the package to maximize the thermal/electrical performance . sufficient clearance should be designed on the pcb between the outer edges of t he land pattern and the inner edges of pad pattern for the leads to avoid any s horts. while the land pattern on the pcb provides a means of heat tran sfer and electrical grounding from t he package to the board through a solder joint, thermal vias are n ecessary to effe ctively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as hea t pipes. the number of vias (i.e. heat pipes) are application specific and dependent upon the package power dissipation as well as electrical conductivity require ments. thus, thermal and electrical analysis and/or testing are recommended to determine the minimu m number needed. maximum thermal an d electrical performance is achieved when an array of vias is incorporated in the land patt ern. it is recommended to use as many v ias connected to ground as possible. it is also recommend ed that the via diameter should b e 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wi cking inside the via during the soldering process which may resu lt in voids in s older between t he exposed pad/slug and the therma l land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recomm endations are to be used as a guideline only. for further information, please refer to the ap plication note on the surface mount as sembly of amkors thermally/ electrically enhance leadframe b ase package, amkor technology. figure 4. p.c. assembly for ex posed pad thermal release path C side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 14 ?2018 integrated device technology, inc. termination for 3. 3v lvpecl outputs the clock layout topology show n below is a typical termination for lvpecl outputs. the two diff erent layouts mentioned are recommended only as guidelines. the differential outputs are a low impedance follower output th at generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc cu rrent path to ground) or current sources must b e used for functionality. these ou tputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency an d minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable c lock layouts ma y exist and it would be recommend ed that the bo ard designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? inp ut 3.3v 3 .3v +_
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 15 ?2018 integrated device technology, inc. termination for 2. 5v lvpecl outputs figure 6a and figure 6b show examples of termination for 2.5v lvpecl driver. these terminatio ns are equivalent to terminating 50 ? to v cc C 2v. for v cc = 2.5v, the v cc C 2v is very close to ground level. the r3 in figure 6b can be eliminated and the terminatio n is shown in figure 6c. figure 6a. 2.5v lvpecl dr iver termination example figure 6c. 2.5v lvpecl dr iver termination example figure 6b. 2.5v lvpecl dr iver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + C 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 + C 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 r318 + C
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 16 ?2018 integrated device technology, inc. power considerations this section provides informat ion on power dissipation and junc tion temperature for the idt8SLVP1104I. equations and example calculations are also provided. 1. power dissipation. the total power dissi pation for the idt8SLVP1104I is the sum of the core power plus the power dissipated due to loading. the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating powe r dissipated due to loading. the maximum current at 85 is as follows: i ee_max = 60ma ? power (core) max = v cc_max * i ee_max = 3.465v * 60ma = 207.9mw ? power (outputs) max = 33.2mw/loaded output pair if all outputs are loaded, the total power is 4 * 33.2mw = 132.8mw total power_ max (3.465v, with all outputs swit ching) = 207.9m w + 132.8mw = 340.7mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire an d bond pad directly affec ts the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperat ure remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambie nt thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate jun ction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer bo ard, the appropriate value is 74.7c/w per tabl e 5 below. therefore, tj for an ambient te mperature of 85c with all outpu ts switching is: 85c + 0.341w * 74.7c/w = 110. 5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded outputs, supply voltage, air flo w and the type of board (multi-layer). table 5. thermal resistance ? ja for 16-lead vfqfpn, forced convection ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 74.7c/ w 65.3c/w 58.5 c/w
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 17 ?2018 integrated device technology, inc. 3. calculations and equations. the purpose of this section is t o calculate the power dissipati on for the lvpecl output pair. lvpecl output driver circuit an d termination are shown in figure 7. figure 7. lvpecl driver c ircuit and termination to calculate power dissipation due to loading, use the followin g equations which assume a 50 ? load, and a termination voltage of v cc C 2v. these are typica l calculations. ? for logic high, v out = v oh_max = v cc_max C 0.7v (v cc_max C v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v cc_max C 1.5v (v cc_max C v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipati on when the output drives low. pd_h = [(v oh_ma C (v cc_ma C 2v))/r l ] * (v cc_ma C v oh_max ) = [(2v C (v cc_max C v oh_max ))/r l ] * (v cc_max C v oh_max ) = [(2v C 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max C (v cc_max C 2v))/r l ] * (v cc_ma C v ol_max ) = [(2v C (v cc_max C v ol_max ))/r l ] * (v cc_max C v ol_max ) = [(2v C 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per ou tput pair = pd_h + pd_l = 33.2mw v out v cc v cc - 2v q1 rl
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 18 ?2018 integrated device technology, inc. reliability information table 6. ? ja vs. air flow table for a 16-lead vfqfpn transistor count the transistor count for the idt8SLVP1104I is: 258 package outline drawings the package outline drawings are appended at the end of this do cument and are accessible from the link below. the package info rmation is the most current data available. www.idt.com/document/psc/16-vfqfp n-package-outline-drawing-30-x -30-x-09-mm-05-mm-170-x-170-mm-epad-nlnlg16p2 ordering information table 7. ordering information ? ja at 0 air flow meters per second 012 . 5 multi-layer pcb, jedec standard te st boards 74.7c/w 65.3c/w 58.5 c/w part/order number marking package shipping packaging temperature 8slvp1104anlgi 104ai lead-free 16-lead vfqfpn tube -40 ? c to 85 ? c 8slvp1104anlgi8 104ai lead-free 16-lead vfqfpn tape & reel -40 ? c to 85 ? c
idt8SLVP1104I datasheet low ph ase noise, 1-to-4, 3.3v, 2.5v lvpecl output fanout buffer idt8slvp1104anlgi march 13, 2018 19 ?2018 integrated device technology, inc. disclaimer integrated device technology, inc. (idt) and its affiliated co mpanies (herein referred to as ?idt?) reserve the right to modify the products and/or specificati ons described herein at any time, without notice, at idt?s sole discretion. perfor mance specifications and operating parameter s of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warra nty of any kind, whether expr ess or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property right s of others. this document is presented only as a guide and does not convey any license under intel- lectual property rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossa ry of common terms, visit www.idt.com/go/glossary . integrated device technology, inc all rights reserved. te ch suppor t www.idt.com/ go/support sa le s 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporat e h e a dqua r t e rs 6024 silver creek valley road san jose, ca 95138 usa www.idt.com revision history revision date description of change march 13, 2018 updated the package outli ne drawings; however, no technical cha nges completed other minor changes february 25, 2014 ordering information: changed tray to tube.
?,qwhjudwhg'hylfh7hfkqrorj\,qf 1 6 -v fqfpn pa c k a ge out line dra w ing 3.0 x 3.0 x 0.9 mm, 0.5mm pitch, 1.70 x 1.70 mm epad nl/nlg16p2, psc-4169-02, rev 05, page 1
?,qwhjudwhg'hylfh7hfkqrorj\,qf 1 6 -v fqfpn pa c k a ge out line dra w ing 3.0 x 3.0 x 0.9 mm, 0.5mm pitch, 1.70 x 1.70 mm epad nl/nlg16p2, psc-4169-02, rev 05, page 2 package revision history rev no. date created description oct 25, 2017 rev 04 remove bookmak at pdf format & update thickness tolerance jan 18, 2018 rev 05 change qfn to vfqfpn

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